Date of Award
2016
Publisher
North Dakota State University
Document Type
Thesis
Degree Awarded
Master of Science (MS)
Program
Electrical and Computer Engineering
Department
Electrical and Computer Engineering
College
Engineering
Faculty Advisor
Wang, Jinhui
Description
Design and fabrication of three-dimensional (3D) ICs is one the newest and hottest trends in semiconductor manufacturing industry. In 3D ICs, multiple 2D silicon dies are stacked vertically, and through silicon vias (TSVs) are used to transfer power and signals between different dies. The electrical characteristic of TSVs can be modeled with equivalent circuits consisted of passive elements. In this thesis, we use “dummy” TSVs as electrical delay units in 3D SRAMs. Our results prove that dummy TSVs based delay units are as effective as conventional delay cells in performance, increase the operational frequency of SRAM up to 110%, reduce the usage of silicon area up to 88%, induce negligible power overhead, and improve robustness against voltage supply variation and fluctuation.
Recommended Citation
Pourbakhsh, Seyed Alireza, "Dummy TSV-Based Timing Optimization for 3D On-Chip Memory" (2016). Electrical and Computer Engineering. 113.
https://digitalcommons.ndsu.edu/elec-comp-eng/113
Rights
NDSU Policy 190.6.2
Rights Link
https://www.ndsu.edu/fileadmin/policy/190.pdf
Author ORCID Identifier
0000-0002-5045-9720
Handle Identifier
https://hdl.handle.net/10365/29093