Date of Award
2019
Publisher
North Dakota State University
Document Type
Dissertation
Degree Awarded
Doctor of Philosophy (PhD)
Program
Electrical and Computer Engineering
Department
Electrical and Computer Engineering
College
Engineering
Faculty Advisor
Smith, Scott C.
Description
Pre-Charge Half Buffers (PCHB) and NULL convention Logic (NCL) are two major commercially successful Quasi-Delay Insensitive (QDI) asynchronous paradigms, which are known for their low-power performance and inherent robustness. In industry, QDI circuits are synthesized from their synchronous counterparts using custom synthesis tools. Validation of the synthesized QDI implementation is a critical design prerequisite before fabrication. At present, validation schemes are mostly extensive simulation based that are good enough to detect shallow bugs, but may fail to detect corner-case bugs. Hence, development of formal verification methods for QDI circuits have been long desired. The very few formal verification methods that exist in the related field have major limiting factors. This dissertation presents different formal verification methodologies applicable to PCHB and NCL circuits, and aims at addressing the limitations of previous verification approaches. The developed methodologies can guarantee both safety (full functional correctness) and liveness (absence of deadlock), and are demonstrated using several increasingly larger sequential and combinational PCHB and NCL circuits, along with various ISCAS benchmarks.
Recommended Citation
Sakib, Ashiq Adnan, "Formal Modeling and Verification Methodologies for Quasi-Delay Insensitive Asynchronous Circuits" (2019). Electrical and Computer Engineering. 120.
https://digitalcommons.ndsu.edu/elec-comp-eng/120
Author ORCID Identifier
0000-0001-7985-2449
Handle Identifier
https://hdl.handle.net/10365/29896