Date of Award
2019
Publisher
North Dakota State University
Document Type
Thesis
Degree Awarded
Master of Science (MS)
Program
Electrical and Computer Engineering
Department
Electrical and Computer Engineering
College
Engineering
Faculty Advisor
Srinivasan, Sudarshan
Description
Sleep Convention Logic (SCL) is an emerging ultra-low power Quasi-Delay Insensitive (QDI) asynchronous design paradigm with enormous potential for industrial applications. Design validation is a critical concern before commercialization. Unlike other QDI paradigms, such as NULL Convention Logic (NCL) and Pre-Charge Half Buffers (PCHB), there exists no formal verification methods for SCL. In this thesis, a unified formal verification scheme for combinational as well as sequential SCL circuits is proposed based on equivalence checking, which verifies both safety and liveness. The method is demonstrated using several multipliers, MACs, and ISCAS benchmarks.
Recommended Citation
Hossain, Mousam, "Formal Verification Methodology for Asynchronous Sleep Convention Logic Circuits Based on Equivalence Verification" (2019). Electrical and Computer Engineering. 96.
https://digitalcommons.ndsu.edu/elec-comp-eng/96
Rights
NDSU policy 190.6.2
Rights Link
https://www.ndsu.edu/fileadmin/policy/190.pdf
Handle Identifier
https://hdl.handle.net/10365/31574